The present invention relates generally to the manufacture of semiconductor devices which include a high-k dielectric gate oxide layer and semiconductor devices obtained thereby. More specifically, the present invention relates to an improved method for performing thermal annealing of high-k dielectric oxide layers and to MOSFET semiconductor devices obtained thereby.
The performance of MOSFET-based semiconductor devices is improved by increasing the capacitance between the gate electrode and the underlying channel region within the semiconductor substrate. Typically, the capacitance is increased by decreasing the thickness of the gate dielectric layer, typically an oxide layer such as a silicon oxide, to below about 100 xc3x85. Currently, silicon oxide, e.g., SiO2, gate dielectric layer thicknesses are approaching about 40 xc3x85 or less. However, the utility of silicon oxide as a gate dielectric is severely limited at such reduced thicknesses, e.g., due to direct tunneling through the gate dielectric layer to the underlying channel region, thereby increasing the gate-to-channel leakage current and an increase in power consumption.
Inasmuch as further reduction in the silicon oxide gate dielectric thickness is impractical in view of the above increase in gate-to-channel leakage current, various approaches have been investigated for reducing the gate-to-channel leakage current while maintaining a thin SiO2 xe2x80x9cequivalent thicknessxe2x80x9d, i.e., the thickness of a non-SiO2 dielectric layer determined by multiplying a given SiO2 thickness by the ratio of the dielectric constant of the non-SiO2 dielectric to that of SiO2, i.e., knon-SiO2/kSiO2. Thus, one approach which has been investigated is the use of materials with dielectric constants higher than that of silicon oxide materials as gate dielectric materials, whereby the xe2x80x9chigh-kxe2x80x9d dielectric materials, i.e., materials with dielectric constants of about 5 or above, replace the conventional silicon oxide-based xe2x80x9clow-kxe2x80x9d dielectric materials with dielectric constants of about 4 or below. The increased capacitance k (or permittivity xcex5) of the gate dielectric material advantageously results in an increase in the gate-to-channel capacitance, which in turn, results in improved device performance. Since the capacitance C is proportional to the permittivity xcex5 of the gate dielectric material divided by the thickness t of the gate dielectric layer, it is evident that the use of a high-k (or high-xcex5) material permits use of thicker gate dielectric layers, i.e.,  greater than 40 xc3x85, whereby both greater capacitance and device speed are obtained with less gate-to-channel leakage current.
Typically, high-k dielectric materials, i.e., with kxe2x89xa75, suitable for use as gate dielectric layers in the manufacture of semiconductor devices, are formed with a physical thickness from about 40 to about 500 xc3x85, typically 40-100 xc3x85 (or a SiO2 equivalent thickness less than about 40 xc3x85), and comprise metal and oxygen-containing material including at least one dielectric material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides. Suitable metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, and yttrium oxide; suitable metal silicates include zirconium silicate, and hafnium silicate; suitable metal aluminates include hafnium aluminate and lanthanum aluminate; suitable metal titanates include lead titanate, barium titanate, strontium titanate, and barium strontium titanate; suitable metal zirconates include lead zirconate; and suitable ferroelectric and/or ternary metal oxides include PST (PbScxTa1xe2x88x92xO3), PZN (PbZnxNb1xe2x88x92xO3), PZT (PbZrxTi1xe2x88x92xO3), and PMN (PbMgxNb1xe2x88x92xO3). Preferred methods for deposition of the high-k metal oxide layer include various chemical vapor deposition (CVD) methods and physical vapor deposition (PVD) methods such as sputtering, vacuum evaporation, etc.
However, the use of high-k metal oxide-based materials as gate dielectric layers for MOSFET semiconductor devices incurs a disadvantage in that such high-k dielectric materials inevitably are formed to contain a much greater number of bulk traps and interface traps (at the interface between the gate dielectric layer and the underlying semiconductor substrate) than gate dielectric layers comprising thermally grown, low-k SiO2. In particular, the presence of traps at the interface between the high-k gate dielectric layer and the underlying semiconductor substrate decreases electron mobility in the channel region of the semiconductor substrate beneath the gate dielectric layer. The traps also adversely affect both the sub-threshold slope and threshold voltage (Vt) operation of the devices.
One approach for improving gate dielectric performance of high-k dielectrics is to limit the effects of the bulk and interface traps by post-dielectric deposition annealing for deactivating the traps, as by rapid thermal annealing (RTA). However, when annealing for trap deactivation is performed by RTA, the structure comprised of a semiconductor substrate, high-k gate dielectric oxide layer, and overlying gate electrode is maintained at an elevated temperature for a sufficiently long interval such that oxygen diffuses from the high-k dielectric oxide layer into the underlying semiconductor layer to form a layer of oxidized semiconductor material at the interface between the gate oxide layer and the semiconductor substrate. Illustratively, and with reference to FIG. 1, when the substrate is a silicon (Si) or Si-containing substrate, a low-k silicon oxide layer, typically a SiO2 layer, is formed at the interface between the semiconductor substrate and the high-k gate oxide layer. The presence of the low-k SiO2 layer beneath the high-k gate oxide layer disadvantageously increases the Effective Oxide Thickness (EOT) of the gate oxide layer, thereby mitigating the benefit attributable to the thin equivalent SiO2 layer thickness provided by use of the high-k dielectric oxide layer.
Accordingly, there exists a need for improved methodology for performing simple, reliable, and rapid annealing of high-k dielectric oxide layers for trap deactivation, performed as part of a process sequence for the manufacture of high performance MOSFET-based semiconductor devices, e.g., NMOS and PMOS transistors and CMOS devices, which methodology avoids the drawbacks and disadvantages associated with the conventionally utilized RTA processing for trap deactivation and provides, inter alia, MOSFET devices with increased gate-to-channel capacitance and performance benefits/enhancements associated therewith.
The present invention, wherein annealing for deactivation of bulk and interface traps associated with gate dielectric layers composed of high-k dielectric oxide materials, e.g., metal oxides, is performed by a laser thermal annealing (LTA) process which eliminates, or at least substantially reduces, oxygen out-diffusion from the high-k dielectric oxide layer resulting in deleterious formation of a layer of low-k oxidized semiconductor material at the gate dielectric layer/semiconductor substrate interface, effectively addresses and solves the need for improved methodology for the manufacture of high performance MOSFET devices with increased gate-to-channel capacitance and performance benefits/enhancements associated therewith. Further, the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components requiring the formation of high quality, low trap density, high-k dielectric oxide layers on semiconductor substrates.
An advantage of the present invention is an improved method for manufacturing a semiconductor device.
Another advantage of the present invention is an improved method for manufacturing a semiconductor device comprising a high-k dielectric oxide layer.
Yet another advantage of the present invention is an improved method for manufacturing a MOSFET semiconductor device including a gate oxide layer comprised of a high-k dielectric oxide.
Still another advantage of the present invention is an improved MOSFET semiconductor device including a gate oxide layer comprised of a high-k dielectric oxide.
Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate having a surface;
(b) forming a gate oxide layer on at least a portion of the surface of the semiconductor substrate and including an interface therewith, the gate oxide layer comprising a high-k dielectric oxide including a plurality of interface traps at the interface;
(c) forming a gate electrode layer on at least a portion of the gate oxide layer; and
(d) thermal annealing the high-k dielectric gate oxide layer to de-activate the interface traps without incurring formation of a low-k dielectric oxide layer at the interface.
According to embodiments of the present invention, step (a) comprises providing a single crystal, polycrystalline, or amorphous silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (Sixe2x80x94Ge) substrate, or a gallium arsenide (GaAs) substrate; and step (b) comprises forming a high-k gate oxide layer having a dielectric constant k of about 5 or greater.
In accordance with particular embodiments of the present invention, step (b) comprises forming a high-k gate oxide layer having a physical thickness from about 40 to about 100 xc3x85, i.e., a SiO2 equivalent thickness of less than about 40 xc3x85.
According to certain embodiments of the present invention, step (b) comprises forming a high-k metal and oxygen-containing layer, e.g., comprising at least one dielectric material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides. Thus, according to embodiments of the present invention, step (b) comprises forming a high-k metal oxide layer comprising at least one material selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, yttrium oxide, zirconium silicate, hafnium silicate, hafnium aluminate, lanthanum aluminate, lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate; ferroelectric oxides, ternary metal oxides, PST (PbScxTa1xe2x88x92xO3), PZN (PbZnxNb1xe2x88x92xO3), PZT (PbZrxTi1xe2x88x92xO3), and PMN (PbMgxNb1xe2x88x92xO3).
Further embodiments of the present invention include forming a high-k gate oxide layer in step (b) which further includes bulk traps; and step (d) further comprises thermal annealing the high-k gate oxide layer to de-activate the bulk traps.
According to embodiments of the present invention, step (c) comprises forming a gate electrode layer comprising at least one electrically conductive material selected from the group consisting of metals, metal silicides, polysilicon, doped polysilicon, and amorphous silicon; and step (d) comprises performing thermal annealing without incurring formation of a low-k dielectric oxide layer having a dielectric constant k of about 4 or less, e.g., a silicon oxide layer.
In accordance with preferred embodiments of the present invention, step (d) comprises performing laser thermal annealing (LTA), e.g., step (d) comprises performing LTA utilizing a gas immersion laser process with an inert gas atmosphere and a laser wavelength from about 200 nm to about 1.25 xcexcm and irradiation fluence from about 0.10 to about 1 Joule/cm2 for an interval sufficient to anneal out defects in the gate oxide layer without incurring: (1) formation of a low-k dielectric oxide layer having a dielectric constant k of about 4 or less and (2) melting of the semiconductor substrate material and/or the gate electrode material.
According to further embodiments of the present invention, the method further comprises the steps of:
(e) patterning the gate electrode layer to form a gate electrode having a pre-selected width and a pair of opposing side edges;
(f) forming a pair of lightly-doped (LDD) source/drain extension regions in the semiconductor substrate by dopant ion implantation utilizing the gate electrode as an implantation mask;
(g) forming insulative sidewall spacers on each of the pair of opposing side edges of the gate electrode; and
(h) forming a pair of heavier-doped source/drain regions in the semiconductor substrate by dopant ion implantation utilizing the gate electrode with the insulative sidewall spacers thereon as an implantation mask;
wherein step (d) is performed after performing step (h) in order to simultaneously activate the implanted dopant ions in the source/drain regions.
Another aspect of the present invention is a MOSFET semiconductor device including a gate oxide layer comprised of a high-k dielectric oxide which has been annealed to de-activate interface and/or bulk traps therein without incurring formation of a low-k dielectric oxide layer at an interface between the gate oxide layer and an underlying semiconductor substrate.
According to embodiments of the present invention, the MOSFET semiconductor device is fabricated by a process comprising the steps of:
(a) providing a semiconductor substrate having a surface;
(b) forming a gate oxide layer on at least a portion of the surface of the semiconductor substrate and including an interface therewith, the gate oxide layer comprising a high-k dielectric oxide including a plurality of interface traps and/or bulk traps therein;
(c) forming a gate electrode layer on at least a portion of the gate oxide layer;
(d) patterning the gate electrode layer to form a gate electrode having a pre-elected width and a pair of opposing side edges;
(e) forming a pair of lightly-doped (LDD) source/drain extension regions in the semiconductor substrate by dopant ion implantation utilizing the gate electrode as an implantation mask;
(f) forming insulative sidewall spacers on each of the pair of opposing side edges of the gate electrode;
(g) forming a pair of heavier-doped source/drain regions in the semiconductor substrate by dopant ion implantation utilizing the gate electrode with the insulative sidewall spacers thereon as an implantation mask; and
(h) thermal annealing the structure formed in steps (a)-(g) to de-activate the interface and/or bulk traps without incurring formation of a low-k dielectric oxide layer at the interface and to simultaneously activate the implanted dopant ions in the source/drain regions.
In accordance with particular embodiments of the present invention,
step (a) comprises providing a single crystal, polycrystalline, or amorphous silicon substrate, or a silicon-on-insulator (SOI) substrate, a germanium substrate, a silicon-germanium substrate, or a gallium arsenide substrate;
step (b) comprises providing a high-k gate oxide layer having a dielectric constant k of about 5 or greater, a physical thickness from about 40 to about 500 xc3x85, a SiO2 equivalent thickness less than about 40 xc3x85, and comprised of a high-k metal and oxygen-containing layer including at least one dielectric material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides;
step (c) comprises forming a gate electrode layer comprising at least one electrically conductive material selected from the group consisting of metals, metal silicides, polysilicon, doped polysilicon, and amorphous silicon; and
step (h) comprises performing laser thermal annealing (LTA) without incurring formation of a low-k dielectric oxide layer having a dielectric constant k of about 4 or less.
Embodiments of the present invention include PMOS and/or NMOS transistors or CMOS devices.